1. Field of the Invention
The present invention relates to a manufacturing technology of semiconductor device, and particularly to a pattern creation method and pattern creation program applicable for lithography process to be carried out using technology called sidewall leaving process, and a mask manufacturing method and a semiconductor device manufacturing method.
2. Description of the Related Art
In recent years, miniaturization and intensified integration of various kinds of semiconductor devices such as LSIs have progressed remarkably. Accompanied by this, the minimum size necessary for a semiconductor circuit pattern has been approaching the same size as a resolution limit size obtained by current lithography technology. Particularly, in an updated development circuit pattern, sometimes, that minimum size has been lower than the current resolution limit size. To meet such a circumstance, applications of various processes for improving the resolution have been proposed.
For example, as a method for forming a miniaturized gate pattern in a logic device such as an ASIC, the following methods are generally well known. According to a first method, using a Levenson phase shift mask including an opening portion such that the phase of passing light is 0° to 180° across a portion corresponding to a gate portion, a dark portion corresponding to the gate portion is produced so as to form a positive resist pattern thereby forming a miniaturized line. According to a second method (resist trimming), by applying slimming process to a resist pattern after lithography process, the gate length at the finishing stage is reduced. According to a third method (hard mask slimming), by transferring a resist pattern to a hard mask after lithography process, the hard mask is slimmed and after that, a gate pattern material is processed.
As a method for forming miniaturized holes, a method of, after a resist pattern is formed, applying heat treatment upon the resist film to induce plastic deformation in order to reduce the hole diameter (thermal flow process) is available. Further, there is also available a method of, after a resist pattern is formed, applying a coating material which mixes with resist resin by heat treatment on the resist pattern and then reducing space between specified patterns by using heating process (RELACS™ process).
However, in any method, the critical resolution pitch is limited by the specification of an optical system of an applied exposure device. That is, assuming that the exposure wavelength of the exposure device is λ μm and numeric aperture of a projection optical system is NA, the critical resolution pitch Pcritical is Pcritical=0.5×λ/NA. In a semiconductor device which requires a high density repetitive pattern such as a memory device, the aforementioned critical resolution pitch limits the integration degree. However, in the field of flash memory devices which has recently progressed remarkably, the pattern has been required to be formed under dimensions exceeding the resolution limit value of optical lithography in order to achieve a large scale request from the market. That is, in the field of the flash memory device, the miniaturization based on conventional optical lithography technology cannot follow up requests from the market and thus, introduction of a novel miniaturization process is indispensable. Thus, to form an ultrafine pattern exceeding the resolution limit of the conventional optical lithography, some novel methods have been proposed, such as a method of disassembling a pattern to plural groups and repeating the exposure process and processing process several times, and a method of carrying out exposure several times using a two-photon absorption resist.
As one of the promising methods of these novel pattern forming processes, so-called sidewall leaving process is available. Then, this sidewall leaving process is largely classified into two kinds of processes, i.e., a line sidewall leaving process and a space sidewall leaving process. Hereinafter, a case of forming a pattern having a convex section like a gate layer by applying the line sidewall leaving process or space sidewall leaving process will be described briefly. First, a case of forming the pattern by the line sidewall leaving process will be described with reference to FIGS. 26A to 26E.
First, as shown in FIG. 26A, there is prepared a semiconductor substrate 101 in which a processing object film 103, which turns to an integrated circuit pattern later, a first hard mask material 104 as a sacrifice film and a resist film 105 are overlaid on a substrate main body 102 successively. Then, after a mask pattern 107 formed on a mask 106 is exposed and transferred to the resist film 105 by ordinary lithography process, the resist film 105 is developed. Consequently, a resist pattern 108 having the same shape as the mask pattern 107 is formed on the first hard mask 104. This resist pattern 108 is formed in a pattern formation area, which finally turns to a concave shape, adjacent to a desired position for forming a convex pattern.
Next, as shown in FIG. 26B, by etching the first hard mask with the resist pattern 108 as a mask, a first hard mask pattern 109 is formed on the processing object film 103. At this time, by applying the slimming process to the resist pattern 108 or the first hard mask pattern 109, the first hard mask pattern 109 is shaped to a pattern finer than the limit of the resolution of the lithography process. Subsequently, the resist film 105 on the first hard mask pattern 109 shaped into the fine pattern is peeled and removed. In the meantime, like the resist pattern 108, the first hard mask pattern 109 is formed in the concave pattern formation area.
Next, a film 110 which turns to a line sidewall pattern is deposited on the processing object film 103 by covering the first hard mask pattern 109. Subsequently, the film 110 is ground up to a substantially the same height as the first hard mask pattern 109 according to CMP method or the like and the film 110 is patterned according to the RIE method or the like. Consequently, as shown in FIG. 26C, a line sidewall pattern 110 is formed such that it surrounds the sidewall portion of the first hard mask pattern 109.
Next, by etching the line sidewall pattern 110 with a high etching resistance and the first hard mask pattern 109 with a low etching resistance, only the first hard mask pattern 109 on the processing object film 103 is removed. Consequently, as shown in FIG. 26D, only the desired line sidewall pattern 110 is left on the processing object film 103.
Next, the processing object film 103 as a fundamental film is etched with the line sidewall pattern 110 left on the processing object film 103 as a mask. Consequently, as shown in FIG. 26E, a desired integrated circuit pattern 111 is formed of the processing object film 103 on the main body 102 of the semiconductor substrate 101. After the integrated circuit pattern 111 is formed, the line sidewall pattern 110 on the processing object film 103 is peeled and removed. If the line sidewall leaving process is used, a gate electrode interconnect pattern 111 as an integrated circuit pattern having a convex shaped section can be formed on the substrate main body 102 through such a process. If the line sidewall leaving process is used, the sidewall pattern for the resist pattern to be formed in lithography process is a design pattern.
Next, a case of forming a pattern through the space sidewall leaving process will be described with reference to FIGS. 27A to 27F. In the meantime, like reference numerals are attached to the same components as the line sidewall leaving process and detailed description thereof is omitted.
Through the same process as the line sidewall leaving process, as shown in FIGS. 27A and 27B, the first hard mask pattern 109 finer than the limit of the resolution of the lithography process is formed on the processing object film 103.
Next, as shown in FIG. 27C, the line sidewall pattern 110 is formed such that it surrounds the first hard mask pattern 109 by the same process as the line sidewall leaving process.
Next, a second hard mask material 112 is deposited on the processing object film 103 by covering the first hard mask pattern 109 and the line sidewall pattern 110. Subsequently, the second hard mask material 112 is ground up to substantially the same height as the first hard mask pattern 109 and the line sidewall pattern 110 according to the CMP method or the like. Consequently, as shown in FIG. 27D, the second hard mask material 112 is buried into the space portion between the line sidewall patterns 110.
Next, by etching the first hard mask pattern 109 and the second hard mask material 112 with a high etching resistance and the line sidewall pattern 110 with a low etching resistance, only the line sidewall pattern 110 on the processing object film 103 is removed. Consequently, as shown in FIG. 27E, a hard mask pattern 113 is formed of the first hard mask pattern 109 and the second hard mask pattern 112. The second hard mask pattern 112 is called space sidewall pattern.
Next, with the hard mask pattern 113 left on the processing object film 103 as a mask, the processing object film 103 as a fundamental film is etched. Consequently, as shown in FIG. 27F, a desired integrated circuit pattern 114 is formed of the processing object film 103 on the main body 102 of the semiconductor substrate 101. After the integrated circuit pattern 114 is formed, the hard mask pattern 113 on the processing object film 103 is peeled and removed. If the space sidewall leaving process is used, a gate electrode interconnect pattern 114 as an integrated circuit pattern having a convex shaped section can be formed on the substrate main body 102 through such a process. If this space sidewall leaving process is adopted, space adjacent to the sidewall portion of the resist pattern formed in lithography process is a space for design pattern.
If the sidewall leaving process is used, necessarily the design pattern is different from the resist pattern formed in the lithography process regardless of the line sidewall leaving process or the space sidewall leaving process. That is, the mask pattern of the photomask for use in the sidewall leaving process is different from a pattern formed finally by the sidewall leaving process. Therefore, to execute the sidewall leaving process, after data of a desired resist pattern is created based on data of the design pattern, data of the resist pattern needs to be converted to data of the mask pattern of a photomask for use in the lithography process. However, such a method which can execute the data conversion rapidly and easily has not been reported.
The sidewall leaving process has such a fault that an unwanted portion is produced in an obtained pattern or a large-area pattern cannot be formed by a single process. For this reason, if the sidewall leaving process is used, after a fundamental pattern is formed, it is necessary to remove the unwanted portion using another mask different from the mask used for pattern formation or transfer a large-area pattern. Further, if an irregular pattern is formed by the sidewall leaving process, data of a pattern to be formed by the sidewall leaving process needs to be created by a device designer in order to create data for removal of surplus pattern. Thus, there occurs a problem in handling data. Further, a problem may occur in data to be created by the device designer.
Assume that a fine line and space pattern is formed into such a staircase configuration that the length of the line pattern is increased or decreased in order as it goes from one side to the other side. In this case, because a surplus pattern is always produced when the sidewall leaving process is adopted, mask exposure for removing that surplus pattern needs to be carried out after the sidewall leaving process. In this case, for the staircase-like line pattern, tolerance (Tol) of mismatch between surplus pattern removal exposure and sidewall pattern exposure needs to be set to a value smaller than the minimum line width of the line pattern. If this tolerance of mismatch is set to a larger value than half of the minimum line width of the line pattern, there is a possibility that a line pattern very much finer than the minimum line width of a desired line pattern may be formed on a wafer when the mismatch is produced. Then, such an extremely fine line pattern can become the cause of a fault.
As disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 2006-186104, the method for removing the surplus pattern using an oblique pattern has such an advantage that the tolerance of mismatch between the surplus pattern removal exposure and sidewall pattern exposure can be set to a value larger than half of the minimum line width of a desired line pattern. However, this method using the oblique pattern requires preliminary setting of oblique pattern data when data of a desired line pattern is designed. Thus, the method using the oblique pattern suffers from a large load for data handling as described above. Thus, in the case of the oblique pattern method, it is desired to remove the surplus pattern using the oblique pattern after tape out of pattern design data for actual applications.